The present invention relates to semiconductor devices and manufacturing methods thereof, and more specifically, to a technique effectively applied to a semiconductor device with a nonvolatile memory and a manufacturing method thereof.
An electrically erasable and programmable read only memory (EEPROM) is widely used as an electrically writable and erasable nonvolatile semiconductor storage device. Such a storage device (memory), typified by a flash memory widely used at present, includes a conductive floating gate electrode or trapping insulating film surrounded by an oxide film, under a gate electrode of a MISFET. The storage device is designed to identify the state of charges stored in the floating gate or trapping insulating film as storage information, and to read the information as a threshold of a transistor. The trapping insulating film is an insulating film that can store the charges, and includes a silicon nitride film, by way of example. The storage device is further designed to shift a threshold of the MISFET by trapping and emission of the charges into and from a charge storage region to act as a storage element. The flash memory includes, for example, a split gate cell using a metal-oxide-nitride-oxide-semiconductor (MONOS) film. This kind of memory has the following advantages by using a silicon nitride film for the charge storage region. For example, such a memory has excellent reliability of data hold because of discontinuously storing the charges as compared to the conductive floating gate film. And, the excellent reliability of the date hold enables the reduction in thickness of oxide films located above and under the silicon nitride film, and can decrease the voltage for writing and erasing operations.
Japanese Unexamined Patent Publication No. 2003-309193 (Patent Document 1) describes a technique regarding a MONOS memory.
Japanese Unexamined Patent Publication No. 2000-22005 (Patent Document 2) discloses a technique regarding a nanocrystal floating gate.
Japanese Unexamined Patent Publication No. 2010-161154 (Patent Document 3) discloses a technique regarding silicon nano-dots.
Japanese Unexamined Patent Publication No. 2011-146612 (Patent Document 4) discloses a technique regarding a MONOS memory.
Non-Patent Document 1 discloses a technique regarding a charge trapping in a MONOS structure.